Low Stress Dielectric Layers for Wafer Level Packages to Reduce Wafer Warpage and Improve Board-Level Temperature-Cycle Reliability


This paper presents a negative-tone photoimageable spin-on dielectric material that is based on a unique molecule for wafer level packaging application.  The molecule is an extended polyimide having photoactive maleimide end groups.   It is an ideal alternative to conventional dielectric materials for solving both the wafer warpage and temperature cycle RDL crack issues.


The trend to bigger wafer size and thinner wafer thickness is aggravating wafer warpage due to residual film stress from the polymer layers on the wafer as shown in Fig. 1.

Larger and thinner wafer aggravates wafer warpage

Conventional dielectric layers used in wafer-level packaging are based on PBO/polyimides that are formed by way of a condensation reaction which requires a “hard bake” step at a temperature of 300°C.

During this condensation reaction, new chemical bonds are formed as the material crosslinks into a thermoset polymer and the fugitive condensate is driven out of the coating to result in high volume shrinkage stress (Fig. 2).

Generalized reaction mechanism of conventional aromatic Polyimide Formation

As the thermoset material cools from “hard bake” temperature to room temperature, CTE mismatch between the thermoset material and silicon induces strain over a large temperature range.   This, coupled with the high modulus of the material, results in high CTE mismatch stress on the wafer. The shrinkage and CTE mismatch stress produce significant wafer warpage on thin and large diameter wafers.

On the other hand, when a finished wafer level package, such as a fan-out WLP, is soldered onto a PCB and subjected to temperature cycling, the solder joints and dielectric layers see CTE mismatch stress between the board and the silicon. High modulus conventional dielectric layers are poor stress absorbers.  With standard SAC solder ball, the cyclic stress manifests itself in fatigue cracking of the solder.   With new solder alloy with improved metallurgical properties, however, the failure mode is shifted to “crack in RDL dielectric layers”.

In addition, the dielectric constants and dielectric dissipation of conventional PI/PBO are relatively high in the low k world.  This is a limiting factor for high-frequency applications.

Molecular level approach

To resolve the above-mentioned problems, a unique imide- extended liquid bis maleimide monomer as shown in the block diagram in Fig. 3 was prepared.

imide-extended liquid bismaleimide monomer

Like conventional polyimides, the molecule uses dianhydrides and diamines to produce the backbone; except the amic acid-to-polyimide conversion is performed in a reactor and the water condensation is extracted. This eliminates the need for the high-temperature hard bake step and high volume shrinkage during cure from the end-user process. Essentially, it removes the stresses associated with the high-temperature hard bake and volume shrinkage. The Generalized reaction mechanism of the conventional aromatic Polyimide Formation
imide functional group is one of the most thermally stable groups known. Thus, the monomer provides a maleimide functionalized thermoset composition without compromising superior thermal stability.

By changing the anhydride and amine starting materials, a wide variety of properties, liquids, rubber-like films, and stiff glassy solids, can be prepared.

For RDL dielectric application, an aliphatic backbone monomer is chosen to yield a low modulus, low Dk/Df, and hydrophobic material when cured.  The formulated material is UV curable, photoimageable, and can be processed using standard wafer coating methods as shown in Fig. 4.

Formulated material can be processed using standard wafer coating method without high temperature hard bake

The surface is non-tacky after spin coating and drying. Imaging is a negative tone and requires 500 mJ/cm2. Crosslinking of the photoimageable monomer occurs when the coating is exposed to  UV  I-line which initiates a  chain reaction that propagates through the  addition of chemical bonds between the photoactive maleimide end groups.   No high temperature “hard bake” is required.  The final step is a “post develop bake” at 125°C to 175°C to remove any remaining solvents and to promote bonding of coupling agents for better adhesion.

Fig. 5 shows exposure of 500 mJ/cm2  provides sufficient cross-linking to achieve >80% thickness.

Residual thickness vs UV energy

Fig. 6 shows the unexposed material can be easily washed away by the developing solvent.

Residual thickness vs develop time

Fig. 7 shows an example of via holes with an aspect ratio of 0.5 (20 μm diameter, 10 μm thickness) on SiN passivation. With further optimization in formulation and equipment setup, the aspect ratio of 2.0 (5 μm diameter, 10 μm thickness) has been reported.

Photolithograph of imide-linked BMI material

As shown in Fig. 8, the overall cure shrinkage is very low compared to conventional materials.   This is because the backbone of the oligomer is fully imidized and no further condensation is required during processing.

Volume shrinkage comparison

The aliphatic backbone yields a low modulus material. As shown in  Table  1,  the material has less than one-tenth modulus of conventional PBO and PI resins.

Once cured, the material contains only thermally stable imide moieties which have similar thermal stability and decomposition temperature compared to conventional polyimide as shown in Fig. 9.

Thermal stability of imide-linked BMI

During photopolymerization, the  BMI  functional units cross-link to become a fully cured thermoset.  No volatiles are generated on the cure.   The cured material is thermally stable at 150°C high-temperature storage.  As shown in Fig. 10, the modulus of the cured film remains stable over 1000 hours.

150°C HTS of imide-linked BMI

Free-radical cure polymerization allows a wide range of coupling agents to be used.   By selecting the appropriate coupling agents, excellent adhesion is obtained on silicon and copper before and after 96 hours of 121°C pressure cooker as measured using the cross-cut adhesion tests following the ISO 2409 method in Fig. 11.

Tape peel test on silicon and copper substrates after 96 hours of PTC

With its hydrophobic backbone, the imide-linked BMI has low moisture uptake.  As shown in Fig. 12, it performs very well in 1000 hour of 85°C /85%RH electrical migration.

Electrical migration test with bias voltage

Table 2 lists the material properties.  As shown, it is a low modulus (260 MPa) material.  It has the high thermal stability (5% weight loss at 428°C) of conventional materials but with the advantage of better high-frequency electrical performance in terms of much lower Dk and Df, and better leakage current and electro-migration in terms of much lower water absorption.

Wafer Warpage

Wafer warpage due  to  film stress can be  explained by

Stoney equation:

r= Es   * Ts2/ (1-v) * 6*σf *Tf


r = radius of curvature of the wafer

Es = Elastic Modulus of silicon,

ts = thickness of the wafer

v = Poisson’s ratio of silicon,

tf = thickness of film

σf = film stress =Ef*εf where

Ef = Elastic Modulus of film

εf = film strain

1. For strain due to CTE mismatch

εf=(αf-αs) ΔT


αf = CTE of film,

αs = CTE of silicon,

ΔT= temperature difference

2. For strain due to Cure shrinkage



ΔV= volume shrinkage

UV curing at near room-temperature results in a much smaller cooling temperature excursion.  As such, the ΔT term in the equation above is small compared to the large temperature excursion between curing at 350°C and testing warpage at 25°C.  Furthermore, since cure shrinkage from the free radical polymerization of BMI is much smaller than from condensation cure, the ΔV term is also small.  The overall film strain εf from UV curing of imide-linked BMI is small and hence the film stress σf is much less than conventional PIs. Since σf is in the denominator of the Radius of Curvature equation, it follows that the radius of curvature is large and wafer warpage is significantly lower than that of conventional wafer coating materials.

As shown in Fig. 13, 200 mm wafers were used for wafer warpage comparison.

Wafer warpage comparison

One wafer was coated with low- temperature cure conventional material and cured at 200°C followed by PDD at 175°C. Cured film thickness was around 10 μm.  Both wafers were thinned to 50 μm using the same back grinding conditions, DISCO DGP8761, #320  #2000  Dry polish.  The 200°C cure material registered 19 mm of warpage while the BMI wafer was almost flat.

Stress Buffering

As a   low modulus   material,  the imide-linked  BMI improves reliability through self-deformation thereby acting as a stress buffer layer.  The deformation of the dielectric layers absorbs cyclic stress during board-level temperature cycle test and mechanical shock during drop test to extend solder joint life.

To demonstrate the stress buffering effect of the low modulus material, stress buffer layers of different thicknesses were added to a BSI CMOS sensor CSP [1].  The CSPs were temperature cycles.  Fig. 14 shows the inclusion of the stress buffer at where soldered bump will be placed.

Using imide-linked BMI as stress buffer layer underneath solder bump

Fig. 15 shows the average resistance measurements during board-level temperature cycling.

Without stress buffer layer, increase in resistance seen before 1000 cycles

As shown, the reference leg that was without any stress buffer layer, started to register an increase in average resistance before 1000 cycles. The three legs with 5μm, 10μm, and 15μm stress buffer layer showed no significant increase.

Fig. 16 is a continuation of the temperature cycle test with an amplified Y axis. As shown, the 5μm started showing an increase in resistance after 4000  cycles,  while the thicker buffer layer legs continued to show low resistance even up to 6000 cycles.

Resistance VS temp cycle

Fig. 17 is a log-log plot on the failure rate.   The solder bump life was estimated to be 4000 cycles with just 5 μm of a stress buffer layer.

Solder bump life of 4000 cycles

Other Applications

As mentioned previously in the molecular design section, a wide variety of imide-linked BMI can be prepared with different properties by changing the anhydride and amine starting materials.    The molecule  in  Fig.  3  can also  be designed to have very low CTE, while maintaining the low Dk and Df advantages.  Table 3 shows the properties of one such molecule.

By dissolving in a solvent, adding thermal initiator and additives, this molecule can be formulated into a filler-free, 175°C thermal cure, low CTE material suitable for polymer collar type of applications to improve drop test performance [2].    Compared to epoxy-based polymer collars,  the  BMI offers high thermal stability, low Dk/Df and low moisture absorption.


Maleimide-terminated aliphatic polyimide has key processing and performance advantages over conventional wafer coating materials while maintaining the high thermal stability and excellent chemical resistance of conventional materials.  The UV cure capability allows the lowest possible wafer warpage at room temperature.  “Post development dry” to driving out residual solvent and improve bonding of coupling agents can be done at the temperature from 125°C to 175°C. The low modulus property of aliphatic backbone is beneficial in making an RDL dielectric layer, doubling up as a stress buffer layer to extend solder life and delay crack initiation. Its excellent dielectric properties (Dk = 2.45, Df =0.001) are beneficial for high frequency WLP.


The authors would like to thank ZyCube Co. for testing the materials; especially to Hirofumi Nakamura san for providing the temperature cycling results and his advice on the interpretation of the test data.


  1. Nakamura,   H.,   “Using three-dimensional packaging technology for automotive image sensor  CSP,”  2196th Electronic Journal, Technical Seminar, Japan, Apr. 2014.
  2. D Bhupinder Singh, Vanessa Smet, Jaesik Lee, Gary Menezes,  Makoto  Kobayashi,  Pulugurtha  Markondeya Raj, Venky Sundaram, Brian Roggeman, Urmi Ray, Riko Radojcic, Rao Tummala, “First Demonstration of Drop- test Reliability of Ultra-thin Glass BGA Packages Directly Assembled on Boards for Smartphone Applications,” 65th IEEE  Electronic Components & Technology Conference, 2015, pp. 1566-1573.

To know more regarding Low-Stress Dielectric Layers for Wafer Level Packages, visit www.caplinq.com. You can also contact us if you any queries regarding CAPLINQ’s adhesive, sealings, and coatings.

About Chris Perabo

Chris is an energetic and enthusiastic engineer and entrepreneur. He is always interested in taking highly technical subjects and distilling these to their essence so that even the layman can understand. He loves to get into the technical details of an issue and then understand how it can be useful for specific customers and applications. Chris is currently the Director of Business Development at CAPLINQ.

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